1. Field of the Invention
The present invention generally relates to thin film transistor array substrates (TFT array substrates) and fabricating methods thereof, and more particularly, to TFT array substrates with high aperture ratio and large storage capacitors and fabricating methods thereof.
2. Description of Related Art
Along with the progresses of photoelectric technology and semiconductor process, a thin film transistor liquid crystal display (TFT-LCD) has played the major role among various display apparatuses. A TFT-LCD mainly comprises a TFT array substrate, a color filter substrate (CF substrate) and a liquid crystal layer. The TFT array substrate includes a plurality of pixel structures arranged in an array, and each of the pixel structures includes a thin film transistor (TFT) and a pixel electrode. To maintain good display quality of the TFT-LCD, a storage capacitor is further formed in each pixel structure.
FIG. 1A is a top view diagram of a conventional TFT array substrate with low-temperature polysilicon TFTs (LTPS-TFT). FIG. 1B is the sectional diagram of FIG. 1A along line A-A′. Referring to FIGS. 1A and 1B, the TFT array substrate 100 includes a substrate 110, a patterned polysilicon layer 120, a first patterned insulating layer 130, a first metal layer 140, a second patterned insulating layer 150, a second metal layer 160, a third patterned insulating layer 170 and a transparent conductive layer 180, and the transparent conductive layer 180 contains a pixel electrode 180a. 
Referring to FIGS. 1A and 1B, the substrate 110 has a pixel region 112 and a bonding pad region 114 located surrounding the pixel region 112. The patterned polysilicon layer 120 is disposed on the substrate 110 and includes a source 122 and a drain 124. The first patterned insulating layer 130 covers the patterned polysilicon layer 120. The first metal layer 140 is disposed on the first patterned insulating layer 130 and includes a gate 142, a scan line 144 electrically connected to the gate 142 and a common electrode 146 disposed within the pixel region 112. The second patterned insulating layer 150 covers the first metal layer 140, and a contact hole 190 is disposed in the first patterned insulating layer 130 and the second patterned insulating layer 150 to expose the drain 124. The second metal layer 160 is disposed on the second patterned insulating layer 150 and is electrically connected to the drain 124 via the contact hole 190. The second metal layer 160 further includes a data line 162 electrically connected to the source 122 via another contact hole 192.
The third patterned insulating layer 170 covers the second metal layer 160 and has a contact hole 194 to expose the second metal layer 160 electrically connected to the drain 124. The pixel electrode 180a is electrically connected to the second metal layer 160 via the contact hole 194, and then electrically connected to the drain 124. As shown in FIG. 1B, the drain 124 within the pixel region 112, the first patterned insulating layer 130, the common electrode 146, the second patterned insulating layer 150 and the second metal layer 160 together form a storage capacitor Cst.
FIG. 1C is a diagram showing a transparent region and an opaque region of the TFT array substrate of FIG. 1A. Referring to FIGS. 1A and 1C, the TFT array substrate 100 has a transparent region 102 and an opaque region 104 therewithin. It can be seen hereinbefore that the area occupied by the metal film layer (i.e., the first metal layer 140 and the second metal layers 160 as shown in FIG. 1A) would be opaque. Especially as shown by FIGS. 1A and 1B, the storage capacitor Cst within the pixel region 112 has the common electrode 146 and the second metal layer 160, so that the area occupied by the storage capacitor Cst becomes the opaque region 104, which largely reduces the aperture ratio of the TFT array substrate 100.
FIG. 2A is a top view diagram of a conventional TFT array substrate with amorphous silicon thin film transistors (a-Si TFTs). FIG. 2B is the sectional diagram of FIG. 2A along line D-D′. The TFT array substrate 200 includes a substrate 210, a first metal layer 220, a first insulating layer 230, a channel layer 240, a second metal layer 250, a second insulating layer 260 and a transparent conductive layer 270, and the transparent conductive layer 270 contains a pixel electrode 270a. 
Referring to FIGS. 2A and 2B, the substrate 210 has a pixel region 212 and a bonding pad region 214 located surrounding the pixel region 212. The first metal layer 220 is disposed on the substrate 210 and includes a gate 222, a scan line 224 electrically connected to the gate 222 and a common electrode 226 located within the pixel region 212. The first insulating layer 230 covers the first metal layer 220. The channel layer 240 is disposed on the first insulating layer 230 over the gate 222. The second metal layer 250 is disposed on the first insulating layer 230, and includes a source 252 and a drain 254 both disposed respectively at two sides of the channel layer 240, and a data line 256 electrically connected to the source 252. The second insulating layer 260 covers the second metal layer 250 and exposes the drain 254. The pixel electrode 270a is disposed on the second insulating layer 260 and electrically connected to the drain 254. Especially as shown by FIGS. 2A and 2B, the common electrode 226 within the pixel region 212, the first insulating layer 230, the second insulating layer 260 and the pixel electrode 270a together form a storage capacitor Cst.
FIG. 2C is a diagram showing a transparent region and an opaque region of the TFT array substrate of FIG. 2A. Referring to FIGS. 2A and 2C, the TFT array substrate 200 has a transparent region 202 and an opaque region 204 therewithin. The area occupied by the metal film layer (i.e., the first metal layer 220 and the second metal layers 250 as shown in FIG. 2A) would be opaque. Especially, the common electrode 226 occupies the most area of the pixel region 212, so that the aperture ratio of the TFT array substrate 200 is largely reduced.
FIG. 3A is a top view diagram of another conventional TFT array substrate with amorphous silicon thin film transistors (a-Si TFTs). FIG. 3B is the sectional diagram of FIG. 3A along line E-E′. Referring to FIGS. 3A and 3B, the TFT array substrate 202 is similar to the TFT array substrate 200 of FIG. 2A, and same components of TFT array substrates 200 and 202 are represented with the same marks. Notice that, the storage capacitor of the TFT array substrate 202 has a different design from that of the TFT array substrate 200.
In the TFT array substrate 202 as shown by FIG. 3B, a common electrode 226, a first insulating layer 230, a second metal layer 250, a second insulating layer 260 and a pixel electrode 270a together form a dual storage capacitor. Because the common electrode 226 is a metal film layer and thereby is opaque, the aperture ratio of the TFT array substrate 202 is reduced. It can be seen from the conventional TFT array substrates 100, 200 and 202 that in order to increase the capacitance of the storage capacitor thereof, the areas of the common electrode 146 and 226 must be enlarged, which consequently reduces the aperture ratios of the TFT array substrates 100, 200 and 202.
FIG. 4A is the sectional diagram of FIG. 1A along line B-B′. FIG. 4B is the sectional diagram of FIG. 1A along line C-C′. Referring to FIGS. 1A and 4A, the TFT array substrate 100 has a scan bonding pad 114a, which includes the substrate 110, the first patterned insulating layer 130, the first metal layer 140, the second patterned insulating layer 150, the third patterned insulating layer 170 and the transparent conductive layer 180. The transparent conductive layer 180 is electrically connected to the first metal layer 140 via a contact hole 172.
Referring to FIGS. 1A and 4B, a data bonding pad 114b includes the substrate 110, the first insulating layer 130, the second insulating layer 150, the second metal layer 160, the third insulating layer 170 and the transparent conductive layer 180. The transparent conductive layer 180 is electrically connected to the second metal layer 160 via the contact hole 172.
Note that, the first metal layer 140 and the second metal layer 160 are usually made of Cr, Mo, AlNd/AlNdN or Mo/Al/Mo. Thus, the surfaces of the first metal layer 140 and the second metal layer 160 are easily oxidized. To solve the oxidizing problem, after forming the first metal layer 140 and the second metal layer 160, usually nitrogen gas is injected so that nitriding metal film layers 140′ and 160′ are formed respectively on the surfaces of the first metal layer 140 and the second metal layer 160.
However, the transparent conductive layer 180 is usually made of indium tin oxide (ITO), and the contact resistances between the ITO and the nitriding metal film layers 140′ and 160′ are quite high. Therefore, the scan bonding pad 114a and the data bonding pad 114b have higher contact resistance, and the electronic signals passing through the scan bonding pad 114a and the data bonding pad 114b are weakened seriously.